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| Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF5251 Rev. 3, 04/2008 MCF5251 MCF5251 ColdFire(R) Microprocessor Data Sheet Package Information MAPBGA-225 Ordering Information: See Table 1 on page 2 1 Introduction This document provides an overview of the MCF5251 ColdFire processor and general descriptions of the MCF5251 features and modules. Also provided are electrical specifications, pin assignments, and package diagrams for MCF5251 ColdFire(R) processor. For functional characteristics, refer to the MCF5251 Reference Manual (MCF5251RM). The MCF5251 is a system controller/decoder for compressed audio music players addressing both portable and automotive solutions supporting CD, HDD and USB based systems. The 32-bit ColdFire core with enhanced multiply and accumulate (eMAC) unit provides optimum performance and code density for the combination of control code and signal processing required for compressed audio decode, file management, and system control. The MCF5251 is a general purpose system controller with over 125 Dhrystone 2.1 MIPS @ 140 MHz performance. The integrated peripherals and EMAC allow the MCF5251 to replace both the microcontroller 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Orderable Part Numbers . . . . . . . . . . . . . . 2 1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 3 2 Functional Description . . . . . . . . . . . . . . . . . . . 4 2.1 Version 2 ColdFire Core . . . . . . . . . . . . . . . 4 2.2 Module Inventory . . . . . . . . . . . . . . . . . . . . 4 3 Signal Description . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical Specifications . . . . . . . . . . . . . . . . . 11 4.1 SDRAM Bus Timing . . . . . . . . . . . . . . . . . 16 4.2 SPDIF Timing . . . . . . . . . . . . . . . . . . . . . . 17 4.3 Serial Audio Interface Timing . . . . . . . . . . 17 4.4 DDATA/PST/PSTCLK Debug Interface . . 17 4.5 BDM and JTAG Timing . . . . . . . . . . . . . . 18 5 Package Information and Pinout . . . . . . . . . . 19 5.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . 19 5.2 Package Drawing . . . . . . . . . . . . . . . . . . . 25 6 Product Documentation . . . . . . . . . . . . . . . . . 33 6.1 Revision History . . . . . . . . . . . . . . . . . . . . 33 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2008. All rights reserved. Introduction and the DSP in certain applications. Most peripheral pins can also be remapped as general purpose I/O pins. Low power features include flexible PLL (with power-down mode) with dynamic clock switching, a hardwired CD ROM decoder, advanced 0.13 m CMOS process technology, 1.2 V core power supply, and on-chip 128K-byte SRAM. MP3 decode requires less than 20 MHz CPU bandwidth and runs from on-chip SRAM. For additional information regarding software drivers and applications, refer to http://www.freescale.com/coldfire. 1.1 Orderable Part Numbers Table 1. Orderable Part Numbers Table 1 lists the orderable part numbers for the MCF5251 processor. Orderable Part Number MCF5251VM140 Maximum Clock Frequency 140 MHz Package Type Operating Temperature Range -20 to +70C MP3 Royalty N/A Part Status 225 MAPBGA -40 to +85C N/A Lead free MCF5251CVM140 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 2 Freescale Semiconductor Introduction 1.2 Block Diagram Figure 1 illustrates the functional block diagram of the MCF5251 processor. Standard ColdFire Peripheral Blocks Debug Module with JTAG Timer Timer Pins I2 C 8K Instruction Cache 5x08 DMA I2C Pins UART (3) 5x08 Interrupt MUX E-bus UART Pins 64K KRAM1 ColdFire CF2 Core 140 MHz 5x08 Arbiter 64K KRAM0 SDRAM Interface E-bus SDRAM SRAM IDE BUFENB1 BUFENB2 "Backdoor" Interface Translator IDE_DIOR SmartMedia FlexCAN Pins IDE_DIOW IDE_IORDY SPI Pins Audio Interface Pins AD IN Pins FlashMedia Pins 2x FlexCAN Controller Interrupt Controller SPI Interface Audio Interfaces AD Logic Memory Stick/SD Interface USB 2.0 OTG Controller USB PHY USB XTAL Oscillator Clock PLL CRIN/CROUT Pins XTAL Oscillator Real-Time Clock RTC Pins USB Analog USB XTAL Pins 16 Kbyte SRAM ARB DMA ATA Controller ATA Pins Figure 1. MCF5251 Block Diagram MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 3 Functional Description 2 2.1 Functional Description Version 2 ColdFire Core The Version 2 ColdFire (CF2) core consists of two independent, decoupled pipeline structures to maximize performance while minimizing core size. The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then executes the required function. 2.2 Module Inventory Table 2. Digital and Analog Modules Table 2 shows an alphabetical listing of the modules in the processor. Block Mnemonic ATA ADC Block Name Functional Grouping Brief Description The ATA block is an AT attachment host interface. Its main use is to interface with IDE hard disc drives and ATAPI optical disc drives. The six-channel ADC is based on the Sigma-Delta concept with 12-bit resolution. Both the analog comparator and digital sections are integrated in the MCF5251. The audio interfaces connect to an internal bus that carries all audio data. Each receiver places its received data on the audio bus and each transmitter takes data from the audio bus for transmission. The audio interface module provides the necessary input and output features to receive and transmit digital audio signals over serial audio interfaces (IIS/EIAJ) and over digital audio interfaces (IEC958). The MCF5251 incorporates a ROM Bootloader, which enables booting from UART, I2C, SPI, or IDE devices. The FlexCan module is a full implementation of the Bosch CAN protocol specification 2.0B, which supports both standard and extended message frames. Three programmable chip-select outputs (CS0/CS4, CS1, and CS2) provide signals that enable glueless connection to external memory and peripheral circuits. There are four fully programmable DMA channels for quick data transfer. Advanced Technology Connectivity Attachment Controller Peripheral Battery Level/Keypad Analog/Digital Converter Audio Bus Analog Input AB Audio Interface Audio Interface Boot ROM Connectivity Peripheral Connectivity Peripheral Connectivity Peripheral Core AIM Audio Interface BROM FlexCAN Bootloader Twin Controller Area Network 2.0B Communication Unit Chip Select Module CSM DMAC Direct Memory Access Controller Module enhanced Multiply Accumulate Module eMAC MBUS MMC/SD The integrated eMAC unit provides a common set of DSP operations and enhances the integer multiply instructions in the ColdFire architecture. Memory Bus Interface Bus Operation The bus interface controller transfers data between the ColdFire core or DMA and memory, peripherals, or other devices on the external bus. Multimedia Card/Secure Digital Interface Flash Memory The interface is Sony(R) Memory Stick(R), SecureDigital, and Multi-Media Card Interface card compatible. Note: The Sony Memory Interface does not support Sony MagicGateTM. MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 4 Freescale Semiconductor Functional Description Table 2. Digital and Analog Modules (continued) Block Mnemonic GPIO GPT IDE Block Name General Purpose I/O Interface General Timer Module Integrated Drive Electronics Instruction Cache Inter IC Communication Module Internal 128-KB SRAM Internal Voltage Regulator Joint Test Action Group Functional Grouping System integration Timer peripheral Connectivity peripheral Core Connectivity peripheral Internal memory Linear regulator Test and debug Brief Description GPIO signals are multiplexed with various other signals. The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer. The IDE hardware consists of bus buffers for address and data and are intended to reduce the load on the bus and prevent SDRAM and Flash accesses from propagating to the IDE bus. The instruction cache improves system performance by providing cached instructions to the execution unit in a single clock cycle. The two-wire I2C bus interfaces, compliant with the Philips I2C bus standard, are bidirectional serial buses that exchange data between devices. The 128-Kbyte on-chip SRAM is split over two banks, SRAM0 (64K) and SRAM1 (64K). It provides single clock-cycle access for the ColdFire core. An internal 1.2 V regulator is used to supply the CPU and PLL sections of the MCF5251, reducing the number of external components required and allowing operation from a single supply rail, typically 3.3 volts. To help with system diagnostics and manufacturing testing, the MCF5251 includes dedicated user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability, often referred to as Joint Test Action Group, or JTAG. The QSPI module provides a serial peripheral interface with queued transfer capability. The RTC is a clock that keeps track of the current time even if the clock is turned off. A background-debug mode (BDM) interface provides system debug. The SDRAM controller provides a glueless interface for one bank of SDRAM, and can address up to 32MB. The controller supports a 16-bit data bus. The controller operates in page mode, non-page mode, and burst-page mode and supports SDRAMs. The SIM provides overall control of the internal and external buses and serves as the interface between the ColdFire core and the internal peripherals or external devices. The SIM is responsible for the two interrupt controllers (setting priorities and levels). And it also configures the GPIO ports. The oscillator operates from an external crystal connected across CRIN and CROUT. The circuit can also operate from an external clock connected to CRIN. The on-chip programmable PLL, which generates the processor clock, allows the use of almost any low frequency external clock (5-35 MHz). INC I2C SRAM LIN JTAG QSPI RTC BDM SDRAMC Queued Serial Peripheral Interface Real-Time Clock Background Debug Interface Synchronous DRAM Memory Controller Connectivity Interface Timer Peripheral Test and debug Peripheral Interface SIM System Integration Module System Integration PLL System Oscillator and System Phase Lock Loop Clocking MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 5 Signal Description Table 2. Digital and Analog Modules (continued) Block Mnemonic UART Block Name Universal Asynchronous Receiver /Transmitter Module USB 2.0 High-Speed On-The-Go Functional Grouping Connectivity Peripheral Brief Description Three UARTs handle asynchronous serial communication. USBOTG Connectivity Peripheral The USB module is used for communication to a PC or communication to slave devices; for example, to download data from a hard disc player to a flash player, and to other devices. 3 Signal Description This chapter describes the MCF5251 input and output signals. The signal descriptions as shown in Table 3 are grouped according to relevant functionality. For additional signal information, see "Chapter 2, Signal Description" in the MCF5251 reference manual. Table 3. MCF5251 Signal Index Signal Name Address A[24:1] A[23]/GPO54 Mnemonic Function 24 address lines--address 23 is multiplexed with GPO54 and address 24 is multiplexed with A20 (SDRAM access only). Bus write enable--indicates if read or write cycle in progress. Output enable for asynchronous memories connected to chip selects Data bus used to transfer word data Row address strobe for external SDRAM Column address strobe for external SDRAM Write enable for external SDRAM Upper byte enable--indicates during write cycle if high byte is written. Lower byte enable--indicates during write cycle if low byte is written. SDRAM chip select SDRAM clock enable SDRAM clock output Input/ Output Out Reset State X Read-write control Output enable Data Synchronous row address strobe Synchronous column address strobe SDRAM write enable SDRAM upper byte enable SDRAM lower byte enable SDRAM chip selects SDRAM clock enable System clock RW OE D[31:16] SDRAS/GPIO59 SDCAS/GPIO39 SDWE/GPIO38 SDUDQM/GPO53 SDLDQM/GPO52 SD_CS0/GPIO60 BCLKE/GPIO63 BCLK/GPIO40 Out Out In/Out Out Out Out Out Out In/Out Out In/Out H negated Hi-Z negated negated negated - - negated - - MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 6 Freescale Semiconductor Signal Description Table 3. MCF5251 Signal Index (continued) Signal Name ISA bus read strobe ISA bus write strobe ISA bus wait signal Chip Selects[2:0] Mnemonic IDE_DIOR/GPIO31 (CS2) IDE_DIOW/GPIO32 (CS2) IDE_IORDY/GPIO33 CS0/CS4 CS1/QSPICS3/GPIO28 Function 1 ISA bus read strobe and 1 ISA bus write strobe--allow connection of an independent ISA bus peripheral, such as an IDE slave device. ISA bus wait line available for both busses Chip selects bits 2 through 0-- enable peripherals at programmed addresses. CS0 provides boot ROM selection. Two programmable buffer enables--allow seamless steering of external buffers to split data and address bus in sections. Transfer Acknowledge signal. Wake-up signal input Clock signal for Dual I2C module operation Serial data port for second I2C module operation Receive serial data input for UART Input/ Output In/Out In/Out In/Out Out In/Out Reset State - - - negated Buffer enable 1 Buffer enable 2 BUFENB1/GPIO29 BUFENB2/GPIO30 In/Out In/Out - - Transfer acknowledge Wake Up Serial Clock Line Serial Data Line Receive Data TA/GPIO12 WAKEUP/GPIO21 SCL0/SDATA1_BS1/GPIO41 SCL1/TXD1/GPIO10 SDA0/SDATA3/GPIO42 SDA1/RXD1/GPIO44 SDA1/RXD1/GPIO44 RXD0/GPIO46 EF/RXD2/GPIO6 SCL1/TXD1/GPIO10 TXD0/GPIO45 XTRIM/TXD2/GPIO0 DDATA3/RTS0/GPIO4 DDATA1/RTS1/SDATA2_BS2/GPIO2 In/Out In In/Out In/Out In - - - - - Transmit Data Transmit serial data output for UART Out - Request-To-Send Clear-To-Send Timer Output IEC958 inputs Signals sent from UART0/1 that it is ready to receive data Out In Out In - - - - Signals sent to UART0/1 that data DDATA2/CTS0/GPIO3 DDATA0/CTS1/SDATA0_SDIO1/GPIO1 can be transmitted to peripheral SDATAO1/TOUT0/GPIO18 EBUIN1/GPIO36 EBUIN2/SCLKOUT/GPIO13 EBUIN3/CMD_SDIO2/GPIO14 QSPICS0/EBUIN4/GPIO15 EBUOUT1/GPIO37 QSPICS1/EBUOUT2/GPIO16 SDATAI1/GPIO17 SDATAI3/GPIO8 Capability of output waveform or pulse generation Audio interfaces to IEC958 inputs IEC958 outputs Serial data in Audio interfaces to IEC958 outputs Audio interfaces to serial data inputs Out In - - MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 7 Signal Description Table 3. MCF5251 Signal Index (continued) Signal Name Serial data out Word clock Mnemonic SDATAO1/TOUT0/GPIO18 SDATAO2/GPIO34 LRCK1/GPIO19 LRCK2/GPIO23 LRCK3/AUDIOCLOCK/GPIO43 SCLK1/GPIO20 SCLK2/GPIO22 SCLK3/GPIO35 EF/RXD2/GPIO6 CFLG/GPIO5 RCK/QSPIDIN/QSPIDOUT/ GPIO26 QSPIDOUT/SFSY/GPIO27 QSPICLK/SUBR/GPIO25 XTRIM/TXD2/GPIO0 MCLK1/GPIO11 QSPICS2/MCLK2/GPIO24 LRCK3/AUDIOCLOCK/GPIO43 EBUIN3/CMD_SDIO2/GPIO14 EBUIN2/SCLKOUT/GPIO13 Function Audio interfaces to serial data outputs Audio interfaces to serial word clocks Input/ Output In/Out Out In/Out Reset State - - Bit clock Audio interfaces to serial bit clocks In/Out - Serial input Serial input Subcode clock Subcode sync Subcode data Clock frequency trim Audio clocks out Audio clock in MemoryStick/ SecureDigital interface Error flag serial in C-flag serial in Audio interfaces to subcode clock Audio interfaces to subcode sync Audio interfaces to subcode data Clock trim control DAC output clocks Optional audio clock input Secure Digital command lane-- MemoryStick interface 2 data I/O Clock out for both MemoryStick interfaces and for Secure Digital In/Out In/Out In/Out In/Out In/Out Out Out - - - - - - - - In/Out In/Out In/Out In/Out In/Out - - - - - DDATA0/CTS1/SDATA0_SDIO1/GPIO1 SecureDigital serial data bit 0-- MemoryStick interface 1 data I/O SCL0/SDATA1_BS1/GPIO41 DDATA1/RTS1/SDATA2_BS2/GPIO2 SecureDigital serial data bit 1-- MemoryStick interface 1 strobe SecureDigital serial data bit 2-- MemoryStick interface 2 strobe Reset output signal SecureDigital serial data bit 3 SDA0/SDATA3/GPIO42 In/Out - MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 8 Freescale Semiconductor Signal Description Table 3. MCF5251 Signal Index (continued) Signal Name AT attachment interface ATA_DIOW (IDE interface) ATA_DIOR ATA_IORDY ATA_DMARQ ATA_DMACK ATA_INTRQ ATA_CS0 ATA_CS1 ATA_A[2:0] ATA_D[15:0] CAN interface CAN0_TX CAN0_RX CAN1_TX CAN1_RX USB PHY interface USBVBUS USBID USBRES USBDN USBDP USB oscillator RTC oscillator AD IN USB_CRIN USB_CROUT RTC_CRIN RTCCROUT ADIN0/GPI52 ADIN1/GPI53 ADIN2/GPI54 ADIN3/GPI55 ADIN4/GPI56 ADIN5/GPI57 ADREF ADOUT/SCLK4/GPIO58 QSPICLK/SUBR/GPIO25 RCK/QSPIDIN/QSPIDOUT/GPIO26 Mnemonic Function ATA write strobe signal ATA read strobe signal ATA I/O ready input ATA DMA request ATA DMA acknowledge ATA interrupt request ATA chip select 0 ATA chip select 1 3-bit ATA address bus 16-bit ATA data bus CAN 0 transmit CAN 0 receive CAN 1 transmit CAN 1 receive USB Vbus input USB ID input USB current programming resistor pin USB DM signalling line USB DP signalling line Connections for USB oscillator crystal (24 MHz) Connections for real-time clock crystal (32.768 kHz) Analog-to-Digital Converter input signals Input/ Output Out Out In In Out In Out Out Out In/Out Out In Out In In In Analog In/Out In/Out In Out In Out In Reset State - - - - - - - - - - - - - - - - - - - - - - AD OUT Analog-to-Digital Converter output signal--connects to ADREF via integrator network. QSPI clock signal QSPI data input In/Out - QSPI clock QSPI data in In/Out In/Out - - MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 9 Signal Description Table 3. MCF5251 Signal Index (continued) Signal Name QSPI data out QSPI chip selects Mnemonic RCK/QSPIDIN/QSPIDOUT/GPIO26 QSPIDOUT/SFSY/GPIO27 QSPICS0/EBUIN4/GPIO15 QSPICS1/EBUOUT2/GPIO16 QSPICS2/MCLK2/GPIO24 CS1/QSPICS3/GPIO28 CRIN CROUT RSTI TEST[2:0] LINOUT LININ Function QSPI data out QSPI chip selects Input/ Output In/Out In/Out Reset State - - System oscillator in System oscillator out Reset In Freescale Test Mode Linear regulator output Linear regulator input System input System output Processor reset input TEST pins. Output of 1.2 V to supply core Input, typically I/O supply (3.3V) In Out In In Out In - - - - - - - Linear regulator ground LINGND High Impedance Debug Data HI_Z Assertion tri-states output signal pins In In/Out DDATA0/CTS1/SDATA0_SDIO1/GPIO1 Display of captured processor data and break-point statuses DDATA1/RTS1/SDATA2_BS2/GPIO2 DDATA2/CTS0/GPIO3 DDATA3/RTS0/GPIO4 PST0/GPIO50 PST1/GPIO49 PST2/INTMON2/GPIO48 PST3/INTMON1/GPIO47 PSTCLK/GPIO51 TCK DSCLK/TRST Indication of internal processor status. Hi-Z Processor Status In/Out Hi-Z Processor clock Test Clock Test Reset/ Development Serial Clock Processor clock output Clock signal for IEEE 1149.1A JTAG Multiplexed signal that is asynchronous reset for JTAG controller. Also, clock input for debug module. Multiplexed signal that is test mode select in JTAG mode and a hardware break-point in debug mode Multiplexed serial input for the JTAG or background debug module. Multiplexed serial output for the JTAG or background debug module Out In In - - - Test Mode Select/Break TMS/BKPT Point Test Data Input/ Development Serial Input Test Data Output/Development Serial Output TDI/DSI In - In - TDO/DSO Out - MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 10 Freescale Semiconductor Electrical Specifications 4 Electrical Specifications Table 4 through Table 10 provide the electrical characteristics for the MCF5251 processor. The remaining figures and tables in this section provide the timing diagrams and the timing parameters for the MCF5251 processor. Table 4 provides the maximum rating parameters for the MCF5251 processor. Table 4. Maximum Ratings Rating Supply Core Voltage Maximum Core Operating Voltage Minimum Core Operating Voltage Supply I/O Voltage Maximum I/O Operating Voltage Minimum I/O Operating Voltage Input Voltage Storage Temperature Range Symbol Vcc Vcc Vcc Vcc Vcc Vcc Vin Tstg Value -0.5 to +2.5 +1.32 +1.08 -0.5 to +4.6 +3.6 +3.0 -0.5 to +6.0 -65 to +150 Units V V V V V V V oC Table 5 provides the recommended operating temperatures for the MCF5251 processor. Table 5. Operating Temperature Characteristic Maximum Operating Ambient Temperature Minimum Operating Ambient Temperature 1 Symbol TAmax TAmin Value +851 -40 Units oC oC This published maximum operating ambient temperature should be used only as a system design guideline. All device operating parameters are guaranteed only when the junction temperature does not exceed 125o C. Table 6 provides the recommended operating supply voltages for the MCF5251 processor. Table 6. Recommended Operating Supply Voltages Pin Name COREVDD PADVDD ADVDD ADGND OSCPADVDD OSCPADGND USBVDD USBVDDP Min 1.08 3.0 3.0 - 3.0 - - - Typ 1.2 3.3 3.3 GND 3.3 GND 3.3 1.2 Max 1.32 3.6 3.6 - 3.6 - - - Unit V V V V V V V V MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 11 Electrical Specifications Table 6. Recommended Operating Supply Voltages (continued) Pin Name USBGND RTCVDDA RTCVSSA PLLCOREVDD PLLCOREGND LININ GND Min - 3.0 - 1.08 - 3.0 - Typ GND - GND 1.2 GND 3.3 GND Max - 4.2 - 1.32 - 3.6 - Unit V V V V V V V Table 7 provides the operating parameters for the linear regulator. Table 7. Linear Regulator Operating Parameters Characteristic Input Voltage (LININ) Output Voltage (LINOUT) Output Current Power Dissipation Load Regulation 10% Iout 90% Iout Power Supply Rejection Symbol Vin Vout Iout Pd - PSRR Min 3.0 1.08 - - - - Typ 3.3 1.2 100 - 50 40 Max 3.6 1.32 150 500 60 - Units V V mA mW mV dB NOTE A pmos regulator is used as a current source in this linear regulator, so a 10 F capacitor (ESR 0... 5 Ohm) is needed on the output pin (LINOUT) to integrate the current. Typically, this requires the use of a tantalum type capacitor. Table 8 provides the measured parameters related to temperature for the linear regulator. Table 8. Linear Regulator--Measured Parameters Related to Temperature Characteristic Input Voltage (LININ) Output Voltage (LINOUT) 100 mA load Current Consumption Power Dissipation Load Regulation 10% Iout 90% Iout Symbol Vin Vout Icc Pd - 125 Min 2.97 oC: Typ 3.3 25 oC: Max 3.63 -40 oC: Units V V mA mW mV 1.16: 1.19 1.22 -40 oC: 44 -40 oC: 131 -40 oC: 25 oC: 56 25 oC: 185 25 oC: 125 oC: 68 125 oC: 247 125 oC: 46 57 70 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 12 Freescale Semiconductor Electrical Specifications Voutput vs Vinput 1.23 1.22 1.21 1.2 1.19 1.18 1.17 1.16 1.15 1.14 1.13 2.97 3.3 Input V olta ge 3.63 Figure 2. Linear Regulator--Voutput vs Vinput Table 9 provides the operating parameters for the ADC DC electrical characteristics. Table 9. Operating Parameters for ADC DC Electrical Characteristics Characteristic Operation Voltage Range for ADC Common Mode Rejection Reference Voltage (external) Input offset voltage Input Hysteresis (ADINx = ADVDD/2) ADC Input Linear Operating Range AD Convertor Error Symbol ADVDD CMR ADREF Voffset Vhyst ADINx Min 3 0 0 - 0.73 0 2 Typ - - - 10 0.78 - Max 3.6 ADVDD-1.1 ADVDD-1.1 - 0.85 ADVDD-1.1 Units V v v mV mV V LSB Note: Software and hardware sampling time is dependent on the external RC network used and the internal CPU Frequency and AD Converter clock divider.See Section 12.4.1 in the MCF5251 Reference Manual for more information. Table 10 provides the DC electrical specifications for the digital pins. Table 10. DC Electrical Specifications (I/O Vcc = 3.3 Vdc + 0.3 Vdc) Characteristic Operation Voltage Range for I/O Input High Voltage Input Low Voltage Reset Threshold Voltage - High Reset Threshold Voltage - Low Reset Input Rise Time Reset Input Fall Time Symbol Vcc VIH VIL RtH TtL nS nS Min 3.0 2 -0.3 2.0 - 10 10 Max 3.6 5.5 0.8 - 0.8 - - Units V V V V V - - MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 13 Electrical Specifications Table 10. DC Electrical Specifications (I/O Vcc = 3.3 Vdc + 0.3 Vdc) (continued) Characteristic Input Leakage Current @ 0.0 V/3.3 V During Normal Operation Hi-Impedance (Three-State) Leakage Current @ 0.0 V/3.3 V During Normal Operation Output High Voltage IOH = 11.9 mA1, 6.3 mA2,3.1 mA3 Output Low Voltage IOL = 7.1m A1, 3.5 mA2, 1.8 mA3 Schmitt Trigger Low to High Threshold Point4 Schmitt Trigger High to Low Threshold Point 4 Symbol Iin ITSI VOH VOL VT+ VTCL Min - - 2.4 - 1.67 1.01 - Max 1 1 - 0.4 1.79 1.15 50 Units A A V V V V pF Load Capacitance: D[31:16], SCLK[4:1], SCLKOUT, EBUOUT[2:1], LRCK[3:1], SDATAO[2:1], CFLG, EF, IDE_DIOR, IDE_DIOW, IDE_IORDY, MCLK1, MCLK2 Load Capacitance: A[24:9], ATA_CS0, ATA_CS1, ATA_A[2:0], ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_D[15:0], SDATAI[3,1] Load Capacitance: A[8:1], ADOUT, ATA_RST BCLK, BCLKE, SDCAS, SDRAS, SDLDQM, SDCS0, SDUDQM, SDWE, BUFENB[2:1], CAN0_TX, CAN1_TX, EBUIN1, RXD[2:0] Load Capacitance: SDA0, SDA1, SCL0, SCL1, CMD_SDIO2, SDATA2_BS2, SDATA1_BS1, SDATA0_SDIO1, CS0/CS4, CS1, OE, RW, TA, TXD[2:0], XTRIM, TDO/DSO, RCK, SFSY, SUBR, SDATA3, TOUT0, QSPID_OUT, QSPICS[3:0], QSPICLK, GPIO[6:5] Load Capacitance: DDATA[3:0], PST[3:0], PSTCLK Capacitance5, Vin = 0 V, f = 1 MHz 1 2 CL 15 40 pF CL - 30 pF CL - 20 pF CL CIN - - 15 6 pF pF 8.0 mA: SCL0, SDA0, SCL1, SDA1, PST[3:0], DDATA[3:0], TDSO, RW, ATA_RST, MCLK1, QSPICS2_MCLK2 4.0 mA: BUFENB1, BUFENB2, EBUOUT1, SCLKOUT, CMDSDIO, IDE_DIOR, IDE_DIOW, TOUT0, RTS[1:0], TXD[1:0], SCLK[4:1], LRCK[4:1], SDATAO1, SDATAO2, QSPICLK, QSPICS0, QSPICS1_EBUOUT2, QSPICS3, QSPIDOUT, RCK, XTRIM, A[8:1], ATA_CS0, ATA_CS1, ATA_A[2:0] 3 2.0 mA: TMS/BKPT, DSI/TDI, TRST/DSCLK 4 SCLK[4:1], SCL0, SCL1, SDA0, SDA1, ATA_DMARQ, ATA_INTRQ, ATA_IORDY 5 Capacitance C is periodically sampled rather than 100% tested. IN MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 14 Freescale Semiconductor Electrical Specifications Figure 3 and Table 11 provide the clock timing diagram and timing parameters. CRIN C5 PSTCLK C6 C7 C6 BCLK C8 C8 Figure 3. Clock Timing Definition NOTE Signals shown in Figure 3 are in relation to the SYSCLK clock. No relationship between signals is implied or intended. Table 11 shows the clock timing parameters. Table 11. Clock Timing Parameters 140 MHz CPU ID Characteristic Min - - C5 C6 C7 C8 CRIN Frequency with external oscillator CRIN Frequency with internal oscillator PSTCLK cycle time PSTCLK duty cycle BCLK cycle time BCLK duty cycle 5.00 5 7 40 14.0 35 Max 33.86 16.94 - 60 - 65 MHz MHz ns % ns % Units MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 15 Electrical Specifications Table 12 shows the CRIN Crystal suggested parameters. Table 12. CRIN Crystal Suggested Parameters Parameter Frequency Frequency Tolerance Frequency Stability Over Operating Temperature Range ESR Shunt Capacitance Load Capacitance Min 5 - - - - - Typ - - - 40 7 18 Max 16.94 50 50 - - - Unit MHz ppm ppm pF pF 4.1 SDRAM Bus Timing The SDRAM bus is a synchronous bus. Propagation delays, set-up times and hold times with respect to the SDRAM clock BCLK are shown in Figure 4 and the parameters provided in Table 13. When BCLK clock is not active, SDRAM interface is not valid and the external bus cannot be used. BCLK D1 data (write) D2 BCLKE, SDXDQM, SDWE, SDCS0, SDRAS, SDCAS D3 A[24:9] D4 data (read) D5 Figure 4. SDRAM Bus Timing Diagram MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 16 Freescale Semiconductor Electrical Specifications Table 13. SDRAM Bus Timing Parameters Timing to 50% Points Maximum ID Characteristic 30 pF Load D1 D2 D3 D4 D5 Propagation delay BCLK rising to data valid Propagation delay BCLK rising to BCLKE, SDLDQM, SDUDQM, SDWE, SDCS0, SDRAS, SDCAS valid Propagation delay BCLK rising to A[24:9] valid Set-up time data valid to BCLK rising Hold time BCLK rising to data valid 7.88 8.7 8.3 0 0.7 40 pF Load 8.8 - 9.2 0 0.7 50 pF Load 9.6 - - 0 0.7 ns ns ns ns ns Units 4.2 SPDIF Timing The Sony/Philips Digital Interface (SPDIF) timing parameters are provided in Table 14. SPDIF timing is totally asynchronous, therefore there is no need for relationship with the clock. Table 14 shows the differences between high-low and low-high propagation delay which is called the skew. Table 14. SPDIF Propagation Skew and Transition Parameters Characteristic EBUIN1, EBUIN2, EBUIN3, EBUIN4: asynchronous inputs, no specs apply EBUOUT1, EBUOUT2 output EBUOUT1, EBUOUT2 output 1 2 Pin Load - 40 pF 20 pF Prop Delay Maximum - - - Skew1 Maximum 0.7 1.5 1.5 Transition2 Rise Maximum - 24.2 13.6 Transition Fall Maximum - 31.3 18.0 Units ns ns ns Skew value does not include the skew introduced by different rise and fall times. Transition times between 10% Vdd and 90% Vdd. 4.3 Serial Audio Interface Timing The Serial Audio Interface fully complies with the Industry standard Philips IIS (InterIC Serial Audio Bus) timings. 4.4 DDATA/PST/PSTCLK Debug Interface Table 15. DDATA/PST/PSTCLK Debug Interface Timing Parameters Characteristic Pin Load 15 pF 15 pF Min -1.0 -- Max -- 4.0 Units ns ns Table 15 provides the timing parameters. PSTCLK clock rise edge to DDATA/PSTDATA1 invalid PSTCLK clock rise edge to DDATA/PSTDATA2 valid MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 17 Electrical Specifications 1 Note that output data may go invalid before rising edge of the clock. To clock data in reliably, you need to sample data, for example, 2 ns before rising edge of clock. 2 Timing figure given takes 50% margin for noise and uncertainty on pin capacitance. Simulated clock-to-data, not taking noise effects into account is 2.7 ns. 4.5 BDM and JTAG Timing Table 16. BDM Interface Timing Parameters Characteristic Clock period for DSCLK clock Set-up time DSI, BKPT, to DSCLK rising edge Hold time DSI, BKPT to DSCLK rising edge Propagation delay DSCLK rising edge to TDO/DSO change 1 Table 16 provides the BDM timing parameters. Min -- 4.0 -- 3T Max 5T1 -- T+ 4.0 4T + 32 Units ns ns ns ns T denotes the CPU clock period. E.g. if the CPU is running at 100 MHz, T = 10 ns Figure 5 provides the JTAG timing diagram and Table 17 provides the JTAG timing parameters. J1 TCK J2A J2B J4 TDI, TMS J5 J3B J3A J6 J7 Boundary Scan Data Input J1 TRST J9 TDO J10 J11 J12 Boundary Scan Data Output Figure 5. JTAG Timing Diagram MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 18 Freescale Semiconductor Package Information and Pinout Table 17. JTAG Timing Parameters ID - J1 J2A J2B J3A J3B J4 J5 J6 J7 J8 J9 J10 J11 J12 TCK Frequency of Operation TCK Cycle Time TCK Clock Pulse High Width TCK Clock Pulse Low Width TCK Fall Time (VIH=2.4 V to VIL=0.5 V) TCK Rise Time (VIL=0.5 v to VIH=2.4 V) TDI, TMS to TCK rising (Input Setup) TCK rising to TDI, TMS Invalid (Hold) Boundary Scan Data Valid to TCK (Setup) TCK to Boundary Scan Data Invalid to rising edge (Hold) TRST Pulse Width (asynchronous to clock edges) TCK falling to TDO Valid (signal from driven or three-state) TCK falling to TDO High Impedance TCK falling to Boundary Scan Data Valid (signal from driven or three-state) TCK falling to Boundary Scan. Data High Impedance Characteristic Min 0 100 25 25 -- -- 8 10 1 10 12 -- 2 -- 1 Max 10 -- -- -- 5 5 -- -- -- -- -- 15 15 15 15 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 Package Information and Pinout This section includes the pin assignment information, contact connection diagram, and the mechanical package drawing. The MCF5251 device is available in the following package: * 225 MAPBGA 13 x 13 mm 0.8 mm pitch package as shown in Figure 6. 5.1 Pin Assignment Table 18 defines all the settings of each pad. See Figure 7 for the ball map of pin locations and Table 20 for the device pin list, sorted by signal identification. Table 18. 225 MAPBGA Pin Assignment Name Drive Type/ Load 1st Strength (pF) Function 2nd Function Pinconfig Register Bit GP Pin Reset Notes Address Bus A1 A2 A3 A4 A5 A6 A7 O / 2 mA O / 2 mA O / 2 mA O / 2 mA O / 2 mA O / 2 mA O / 2 mA 30 30 30 30 30 30 30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - X X X X X X X H 3 H 2 H 1 H 5 G 1 G 3 G 2 - - - - - - - MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 19 Package Information and Pinout Table 18. 225 MAPBGA Pin Assignment (continued) Name A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20/A24 A21 A22 A23/GPO54 Drive Type/ Load 1st Strength (pF) Function O / 2 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA O / 8 mA 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 2nd Function - - - - - - - - - - - - A24 Pinconfig Register Bit - - - - - - - - - - - - 31 GP Pin - - - - - - - - - - - - - - - O54 Reset X X X X X X X X X X X X X X X X H 4 Notes - - - - - - - - - - - - Audio Clock Select: 1-LRCK3 pin; 0-CRIN pin - - - - - - - - - - - - A20 H 6 F 2 G 5 F 3 F 1 E 1 G 4 E 2 F 4 E 3 F 5 F 6 - - A23 - - - - - - D 3 D 1 - - Boot Mode Select:1-Memory connected to CS0; 0-Internal boot rom D 2 Data Bus D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 - - - - - - - - - - - - - - - - - - TA BUFENB1 BUFENB2 IDE_DIOR IDE_DIOW IDE_IORDY - - - - - - - - - - - - - - - - Bus Control - - - - - - - - Chip Selects CS4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IO12 IO29 IO30 IO31 IO32 IO33 HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z C 1 E 4 E 5 B 1 C 2 D 4 C 3 B 2 A 2 B 3 A 3 C 4 B 4 D 5 A 4 C 5 - - - - - - - - - - - - - - - - - - - - - Controlled by CS2 registers Controlled by CS2 registers OE RW TA/GPIO12 BUFENB1/GPIO29 BUFENB2/GPIO30 IDE_DIOR/GPIO31 IDE_DIOW/GPIO32 IDE_IORDY/GPIO33 O / 4 mA O / 4 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA 30 30 30 30 30 30 30 30 Negated H R 3 J 4 - - - - - - Negated N 5 P 5 K 6 M 5 P 4 R 4 - Boot Mode Select:1-CS0; 0-CS4 CS0/CS4 O / 4 mA 30 CS0 - J 3 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 20 Freescale Semiconductor Package Information and Pinout Table 18. 225 MAPBGA Pin Assignment (continued) Name CS1/QSPICS3/ GPIO28 Drive Type/ Load 1st Strength (pF) Function IO / 2 mA 30 CS1 2nd Function QSPICS3 Pinconfig Register Bit 25 GP Pin Reset M 7 Notes - IO28 Negated SDRAM Controller BCLK/GPIO40 BCLKE/GPIO63 SDLDQM/GPO52 SDUDQM/GPO53 SDWE/GPIO38 SDCS0/GPIO60 SDRAS/GPIO59 SDCAS/GPIO39 IO / 8 mA IO / 8 mA O / 8 mA O / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA 15 20 20 20 20 20 20 20 BCLK BCLKE SDLDQM SDUDQM SDWE SDCS0 SDRAS SDCAS - - - - - - - - ATA Interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IO40 IO63 O52 O53 - - - - B 5 E 6 C 6 A 5 IO38 Negated IO60 Negated IO59 Negated IO39 Negated C 7 B 6 A 6 D 6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Main Processor Clock Input Main Processor Clock Output Real Time Clock (32.768 kHz) Input Real Time Clock (32.768 kHz) Output ATA_A0 ATA_A1 ATA_A2 ATA_D0 ATA_D1 ATA_D2 ATA_D3 ATA_D4 ATA_D5 ATA_D6 ATA_D7 ATA_D8 ATA_D9 ATA_D10 ATA_D11 ATA_D12 ATA_D13 ATA_D14 ATA_D15 ATA_CS0 ATA_CS1 ATA_DIOR ATA_DIOW ATA_IORDY ATA_INTRQ ATA_DMARQ ATA_DMACK ATA_RST O / 2 mA O / 2 mA O / 2 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA IO / 8 mA O / 2 mA O / 2 mA O / 8 mA O / 8 mA I I I O / 8 mA O / 2 mA 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 - - - 40 40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - A 8 B 7 B 8 B 9 A 9 F 8 F 9 B 1 0 C 1 0 A 1 0 D 1 0 D 1 1 B 1 1 C 1 1 A 1 1 A 1 2 E 1 1 B 1 2 D 1 2 C 9 D 9 B 1 5 A 1 3 D 7 D 8 A 7 C 1 2 C 8 Clock Generation CRIN CROUT RTC_CRIN RTCCROUT - - A A - - - - M 3 N 2 J 1 K 2 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 21 Package Information and Pinout Table 18. 225 MAPBGA Pin Assignment (continued) Name USB_CRIN USB_CROUT XTRIM/TXD2/GPIO0 Drive Type/ Load 1st Strength (pF) Function A A IO / 2 mA 2nd Function - - TXD2 Pinconfig Register Bit - - 0 GP Pin - - IO0 Reset - - - - - - - - - - HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z HI_Z L 1 4 L 1 5 R 6 Notes USB Clock (24 MHz) Input USB Clock (24 MHz) Output Interrupt Capable Input - - 30 - - XTRIM JTAG/BDM/Test TDO/DSO TDI/DSI TMS/BKPT TCK TRST/DSCLK HI_Z PSTCLK/GPIO51 PST0/GPIO50 PST1/GPIO49 PST2/INTMON2/ GPIO48 PST3/INTMON1/ GPIO47 DDATA0/CTS1/ SDATA0_SDIO1/GPIO1 DDATA1/RTS1/ SDATA2_BS2/GPIO2 DDATA2/CTS0/GPIO3 DDATA3/RTS0/GPIO4 TEST0 TEST1 TEST2 O / 4 mA I I I I I IO / 8 mA IO / 4 mA IO / 4 mA IO / 4 mA IO / 4 mA IO / 4 mA IO / 4 mA IO / 4 mA IO / 4 mA I I I 30 - - - - - 30 30 30 30 30 30 30 30 30 - - - - - - PSTCLK PST0 PST1 PST2 PST3 DDATA0 DDATA1 DDATA2 DDATA3 - - - - - - - - - INTMON2 INTMON1 CTS1/SDATA 0_SDIO1 RTS1/SDATA 2_BS2 CTS0 RTS0 - - - - - - - - - 17 18 14,13 24,23 22 21 - - - - - - IO51 IO50 IO49 IO48 IO47 IO1 IO2 IO3 IO4 G 1 3 F 1 5 F 1 2 F 1 3 F 1 4 B 1 3 See TEST0 Description See TEST0 Description See TEST0 Description - See TEST0 Description For Normal Operation Tie This Pin High G 1 4 G 1 5 G 1 2 H 1 4 - - - - - Interrupt Capable Input Interrupt Capable Input Interrupt Capable Input Interrupt Capable Input BDM/JTAG Select: 1-BDM; 0-JTAG For normal operation, tie this pin low. For normal operation, tie this pin low. H 1 3 K 1 0 R 1 1 J 1 4 J 1 2 F 1 1 G 1 0 - - - - - - - - - Reset/Wake-up - - - - - - - - - H 1 0 RSTI WAKEUP/GPIO21 I IO / 2 mA - 30 - WAKEUP - - USB - - - - - - - Audio Interface - TOUT0 - - - - - - - - - - 8 - IO21 - - - - - - - - - - - - - - - E 1 5 R 5 - - - - - - - - - - - - - - - USBDN USBDP USBID USBVBUS USBRES TESTOUT1 NC A A I A A O - IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA - - - - - - - 30 30 30 30 30 30 - - - - - - - SDATAI1 SDATAO1 SCLK1 LRCK1 SDATAO2 SCLK2 - - - - - - - IO17 IO18 IO20 IO19 IO34 IO22 N 1 5 M 1 5 M 1 1 N 1 4 M 1 4 P 1 3 R 1 4 SDATAI1/GPIO17 SDATAO1/TOUT0/ GPIO18 SCLK1/GPIO20 LRCK1/GPIO19 SDATAO2/GPIO34 SCLK2/GPIO22 N 9 R 8 - - - - - - - - K 8 P 8 D 1 5 E 1 3 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 22 Freescale Semiconductor Package Information and Pinout Table 18. 225 MAPBGA Pin Assignment (continued) Name LRCK2/GPIO23 SDATAI3/GPIO8 SCLK3/GPIO35 LRCK3/AUDIOCLK/ GPIO43 EBUIN1/GPIO36 EBUIN2/SCLKOUT/ GPIO13 EBUIN3/ CMD_SDIO2/GPIO14 QSPICS0/EBUIN4/ GPIO15 EBUOUT1/GPIO37 QSPICS1/ EBUOUT2/GPIO16 CFLG/GPIO5 EF/RXD2/GPIO6 MCLK1/GPIO11 QSPICS2/MCLK2/ GPIO24 Drive Type/ Load 1st Strength (pF) Function IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 2 mA IO / 4 mA IO / 4 mA 30 30 30 30 30 30 30 30 30 30 30 30 30 30 LRCK2 SDATAI3 SCLK3 LRCK3 EBUIN1 EBUIN2 EBUIN3 QSPICS0 EBUOUT1 QSPICS1 CFLG EF MCLK1 QSPICS2 2nd Function - - - AUDIOCLK Pinconfig Register Bit - - - - - 16 15 30 GP Pin IO23 IO8 IO35 IO43 IO36 IO13 IO14 IO15 IO37 IO16 IO5 IO6 IO11 IO24 Reset - - - - - - - - - - - - - - E 1 4 N 1 0 R 1 0 M 1 0 Notes - - - See A20/A24 Description - SCLKOUT CMDSDIO2 EBUIN4 N 6 M 6 - - - - - - Interrupt Capable Input Interrupt Capable Input K 7 R 7 - EBUOUT2 - 29 P 6 N 8 - RXD2 - MCLK2 - - - 28 M 9 R 9 D 1 4 P 9 - - Analog-to-Digital Converter ADIN0/GPI52 ADIN1/GPI53 ADIN2/GPI54 ADIN3/GPI55 ADIN4/GPI56 ADIN5/GPI57 ADREF ADOUT/SCLK4/ GPIO58 A A A A A A A IO / 2 mA - - - - - - - 30 ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 ADIN5 - ADOUT - - - - - - - SCLK4 - - - - - - - 9 I52 I53 I54 I55 I56 I57 - IO58 - - - - - - - - K 3 L 1 L 2 L 3 M 1 J 6 M 2 J 5 - - - - - - - - FlexCAN CAN0_TX CAN0_RX CAN1_TX CAN1_RX O / 8 mA I O / 8 mA I 30 - 30 - 30 30 30 - - - - QSPICLK RCK QSPIDOUT - - - - QSPI SUBR QSPIDIN/ QSPIDOUT SFSY - - - - 27 26 10 - - - - IO25 IO26 IO27 - - - - - - - C 1 5 D 1 3 C 1 4 E 1 2 - - - - - - - QSPICLK/SUBR/ GPIO25 RCK/QSPIDIN/ QSPIDOUT/GPIO26 QSPIDOUT/SFSY/ GPIO27 IO / 2 mA IO / 2 mA IO / 2 mA P 7 N 7 M 8 I2C SDA0/SDATA3/ GPIO42 SCL0/SDATA1_BS1/ GPIO41 SDA1/RXD1/GPIO44 IO / 4 mA IO / 4 mA IO / 4 mA 30 30 30 SDA0 SCL0 SDA1 SDATA3 SDATA1_BS1 RXD1 11 12 19 IO42 IO41 IO44 - - - K 9 - - - P 1 0 J 1 5 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 23 Package Information and Pinout Table 18. 225 MAPBGA Pin Assignment (continued) Name SCL1/TXD1/GPIO10 Drive Type/ Load 1st Strength (pF) Function IO / 4 mA 30 SCL1 2nd Function TXD1 Pinconfig Register Bit 20 GP Pin IO10 Reset - - - - - - - - - - - - - - - - - - J 1 3 Notes - - - 3.3 Volt Supply Required 1.2 Volt Output (Approx 50% Efficient) UART TXD0/GPIO45 RXD0/GPIO46 IO / 2 mA IO / 2 mA 30 30 TXD0 RXD0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IO45 IO46 H 1 2 H 1 5 Power/Ground Pins LININ LINOUT LINGND PLLCOREVDD (3 Balls) PLLCOREGND (3 Balls) USBVDD (2 Balls) USBVDDP USBGND (3 Balls) OSCPADVDD OSCPADGND RTC_VDDA RTCVSSA ADVDD ADGND PADVDD (10 Balls) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - A 1 4 B 1 4 C 1 3 S e e N ot e s S e e N ot e s S e e N ot e s L 1 2 S e e N ot e s N 1 - 1.2 Volt Supply Required (M4, N3, P2) N4,P3,R2 3.3 Volt Supply Required (L13, M13) 1.2 Volt Supply Required K11, L11, M12 3.3 Volt Supply Required P 1 - 3.3 Volt Supply Required J 2 K 1 - 3.3 Volt Supply Required K 4 L 4 - 3.3 Volt Supply Required (E7, E9, F10, H8, H11, K5, L6, L8, L10, R13) 1.2 Volt Supply Required (G8, H7, H9, J8) A1, A15, E8, E10, F7, G6, G7, G9, G11, J7, J9, J10, J11, L5, L7, L9, R1, R15 S e e N ot e s COREVDD (4 Balls) COREVSS/PADVSS (18 Balls)2 1 2 - - - - - - - - - - - - - - S e e N ot e s S e e N ot e s For test purposes only. Leave ball as open circuit. These pads are listed as "GND" in the ball map and the rest of the tables. MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 24 Freescale Semiconductor Package Information and Pinout Figure 6 shows the package outline diagram for the MCF5251 processor. 5.2 Package Drawing MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 25 Package Information and Pinout TOP VIEW BOTTOM VIEW Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14. 5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. SIDE VIEW 4. Datum A, the seating plane, is determined by the spherical crown of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. Figure 6. MCF5251 Package Drawing MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 26 Freescale Semiconductor Package Information and Pinout 5.2.1 1 GND MAPBGA Pinout 3 D26 Figure 7 shows the MCF5251 ball map of pad locations. 2 D24 4 D30 5 SDUDQM/ GPO53 BCLK/ GPIO40 D31 6 SDRAS/ GPIO59 SDCS0/ GPIO60 SDLDQM/ GPO52 SDCAS/ GPIO39 BCLKE/ GPIO63 A20/A24 7 ATA_DMAR Q ATA_A1 SDWE/ GPIO38 8 ATA_A0 9 ATA_D1 10 ATA_D6 11 ATA_D11 12 ATA_D12 13 ATA_DIOW 14 LININ 15 GND D19 D23 D25 D28 ATA_A2 ATA_D0 ATA_D4 ATA_D9 ATA_D14 ATA_DMAC K ATA_D15 HI_Z LINOUT ATA_DIOR D16 D20 D22 D27 ATA_RST ATA_CS0 ATA_D5 ATA_D10 LINGND CAN1_TX MCLK1/ GPIO11 LRCK2/ GPIO23 TRST/ DSCLK PSTCLK/ GPIO51 PST2/ INTMON2/ GPIO48 DDATA2/ CTS0/ GPIO3 N/C CAN0_TX SDATAO2/ GPIO34 RSTI A22 A23/GPO54 A21 D21 D29 ATA_IORDY ATA_INTRQ ATA_CS1 ATA_D7 ATA_D8 CAN0_RX SCLK2/ GPIO22 TCK A14 A16 A18 D17 D18 PADVDD GND PADVDD GND ATA_D13 CAN1_RX A13 A10 A12 A17 A19 GND ATA_D2 ATA_D3 PADVDD TEST0 TMS/BKPT PST1/ GPIO49 TXD0/ GPIO45 DDATA3/ RTS0/ GPIO4 N/C TDI/DSI PST0/ GPIO50 RXD0/ GPIO46 A5 A7 A6 A15 A11 GND GND COREVDD GND TEST1 GND TDO/DSO PST3/ INTMON1/ GPIO47 SCL1/TXD1/ GPIO10 A3 A2 A1 A8 A4 ADOUT/ SCLK4/ GPIO58 PADVDD A9 ADIN5/ GPI57 BUFENB2/ GPIO30 COREVDD PADVDD COREVDD TEST2 PADVDD TC_CRIN RTC_VDDA CS0/CS4 RW GND EBUIN3/CM D_SDIO2/ GPIO14 GND COREVDD GND SDA0/ SDATA3/ GPIO42 GND CFLG/ GPIO5 SDATAI1/ GPIO17 GND DDATA0/ CTS1/SDAT A0_SDIO1/ GPIO1 PADVDD LRCK3/ AUDCLK/ GPIO43 SDATAI3/ GPIO8 GND SDA1/RXD1 /GPIO44 TCVSSA RTCCROUT ADIN0/ GPI52 ADIN3/ GPI55 CRIN PLLCORE VDD ADVDD SCLK1/ GPIO20 USBGND N/C N/C ADIN1/ GPI53 ADIN4/ GPI56 OSCPAD VDD OSCPAD GND ADIN2/ GPI54 ADREF ADGND PLLCORE VDD PLLCORE GND GND PADVDD PADVDD USBGND USBVDDP USBVDD USB_CRIN USB_CROU T USBDP EBUIN2/ IDE_DIOR/ SCLKOUT/ GPIO31 GPIO13 TA/GPIO12 EBUIN1/ GPIO36 QSPIDOUT/ CS1/ QSPICS3/ SFSY/ GPIO28 GPIO27 RCK/QSPID QSPICS1/ IN/QSPIDO EBUOUT2/ UT/GPIO26 GPIO16 QSPICLK/ SUBR/ GPIO25 QSPICS0/ EBUIN4/ GPIO15 LRCK1/ GPIO19 SDATAO1/ TOUT0/ GPIO18 USBID USBGND USBVDD USBRES CROUT PLLCORE VDD PLLCORE GND N/C N/C N/C USBVBUS USBDN PLLCORE IDE_DIOW/ BUFENB1/ EBUOUT1/ GPIO32 GPIO29 GPIO37 GND IDE_IORDY/ WAKEUP/ GPIO33 GPIO21 XTRIM/ TXD2/ GPIO0 QSPICS2/ SCL0/SDAT MCLK2/ A1_BS1/ GPIO24 GPIO41 EF/RXD2/ GPIO6 SCLK3/ GPIO35 N/C DDATA1/RT S1/SDATA2 _BS2/ GPIO2 N/C TESTOUT N/C N/C GND OE N/C PADVDD NC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 7. MCF5251 Ball Map Table 19 shows the signal color and signal name legend. Table 19. Signal Color/Name Legend Color None Name Signal name as listed GND PADVDD MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 27 Package Information and Pinout Table 19. Signal Color/Name Legend (continued) Color Name COREVDD USBGND Table 20 shows the device pin list, sorted by signal identification. 3 Table 20. MCF5251 13 x 13 BGA (225 Signal ID by Pad Grid Location) Signal ID A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20/A24 A21 A22 A23/GPO54 A3 A4 A5 A6 A7 A8 A9 ADGND ADIN0/GPI52 ADIN1/GPI53 ADIN2/GPI54 ADIN3/GPI55 ADIN4/GPI56 ADIN5/GPI57 ADOUT/SCLK4/GPIO58 ADREF ADVDD ATA_A0 ATA_A1 ATA_A2 ATA_CS0 ATA_CS1 Pad Location H03 F02 G05 F03 F01 E01 G04 E02 F04 E03 F05 H02 F06 D03 D01 D02 H01 H05 G01 G03 G02 H04 H06 L04 K03 L01 L02 L03 M01 J06 J05 M02 K04 A08 B07 B08 C09 D09 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 28 Freescale Semiconductor Package Information and Pinout Table 20. MCF5251 13 x 13 BGA (225 Signal ID by Pad Grid Location) (continued) Signal ID ATA_D0 ATA_D1 ATA_D10 ATA_D11 ATA_D12 ATA_D13 ATA_D14 ATA_D15 ATA_D2 ATA_D3 ATA_D4 ATA_D5 ATA_D6 ATA_D7 ATA_D8 ATA_D9 ATA_DIOR ATA_DIOW ATA_DMACK ATA_DMARQ ATA_INTRQ ATA_IORDY ATA_RST BCLK/GPIO40 BCLKE/GPIO63 BUFENB1/GPIO29 BUFENB2/GPIO30 CAN0_RX CAN0_TX CAN1_RX CAN1_TX CFLG/GPIO5 COREVDD COREVDD COREVDD COREVDD CRIN CROUT CS0/CS4 CS1/QSPICS3/GPIO28 D16 D17 D18 D19 D20 D21 Pad Location B09 A09 C11 A11 A12 E11 B12 D12 F08 F09 B10 C10 A10 D10 D11 B11 B15 A13 C12 A07 D08 D07 C08 B05 E06 P05 K06 D13 C15 E12 C14 M09 G08 H07 H09 J08 M03 N02 J03 M07 C01 E04 E05 B01 C02 D04 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 29 Package Information and Pinout Table 20. MCF5251 13 x 13 BGA (225 Signal ID by Pad Grid Location) (continued) Signal ID D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DDATA0/CTS1/SDATA0_SDIO1/GPIO1 DDATA1/RTS1/SDATA2_BS2/GPIO2 DDATA2/CTS0/GPIO3 DDATA3/RTS0/GPIO4 EBUIN1/GPIO36 EBUIN2/SCLKOUT/GPIO13 EBUIN3/CMD_SDIO2/GPIO14 EBUOUT1/GPIO37 EF/RXD2/GPIO6 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HI_Z IDE_DIOR/GPIO31 IDE_DIOW/GPIO32 IDE_IORDY/GPIO33 LINGND LININ LINOUT LRCK1/GPIO19 LRCK2/GPIO23 Pad Location C03 B02 A02 B03 A03 C04 B04 D05 A04 C05 K10 R11 J14 J12 N06 M06 K07 P06 R09 A01 A15 E08 E10 F07 G06 G07 G09 G11 J07 J09 J10 J11 L05 L07 L09 R01 R15 B13 M05 P04 R04 C13 A14 B14 P08 E14 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 30 Freescale Semiconductor Package Information and Pinout Table 20. MCF5251 13 x 13 BGA (225 Signal ID by Pad Grid Location) (continued) Signal ID LRCK3/AUDIOCLK/GPIO43 MCLK1/GPIO11 NC OE OSCPADGND OSCPADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PLLAVDD PLLCOREGND PLLCOREGND PLLCOREGND PLLCOREVDD PLLCOREVDD PST0/GPIO50 PST1/GPIO49 PST2/INTMON2/GPIO48 PST3/INTMON1/GPIO47 PSTCLK/GPIO51 QSPICLK/SUBR/GPIO25 QSPICS0/EBUIN4/GPIO15 QSPICS1/EBUOUT2/GPIO16 QSPICS2/MCLK2/GPIO24 QSPIDOUT/SFSY/GPIO27 RCK/QSPIDIN/QSPIDOUT/GPIO26 RSTI RTC_CRIN RTC_VDDA RTCCROUT RTCVSSA RW RXD0/GPIO46 SCL0/SDATA1_BS1/GPIO41 SCL1/TXD1/GPIO10 SCLK1/GPIO20 SCLK2/GPIO22 SCLK3/GPIO35 SDA0/SDATA3/GPIO42 Pad Location M10 D14 R14 R03 P01 N01 E07 E09 F10 H08 H11 K05 L06 L08 L10 R13 M04 N04 P03 R02 N03 P02 G15 G12 H14 H13 G14 P07 R07 N08 P09 M08 N07 E15 J01 J02 K02 K01 J04 H15 P10 J13 K08 E13 R10 K09 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 31 Table 20. MCF5251 13 x 13 BGA (225 Signal ID by Pad Grid Location) (continued) Signal ID SDA1/RXD1/GPIO44 SDATAI1/GPIO17 SDATAI3/GPIO8 SDATAO1/TOUT0/GPIO18 SDATAO2/GPIO34 SDCAS/GPIO39 SDCS0/GPIO60 SDLDQM/GPO52 SDRAS/GPIO59 SDUDQM/GPO53 SDWE/GPIO38 TA/GPIO12 TCK TDI/DSI TDO/DSO TEST0 TEST1 TEST2 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Pad Location J15 N09 N10 R08 D15 D06 B06 C06 A06 A05 C07 N05 F13 F15 G13 F11 G10 H10 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2005, 2006, 2008. All rights reserved. Document Number: MCF5251 Rev. 3 04/2008 Product Documentation Table 20. MCF5251 13 x 13 BGA (225 Signal ID by Pad Grid Location) (continued) Signal ID TESTOUT TMS/BKPT TRST/DSCLK TXD0/GPIO45 USB_CRIN USB_CROUT USBDN USBDP USBGND USBGND USBGND USBID USBRES USBVBUS USBVDD USBVDD USBVDDP WAKEUP/GPIO21 XTRIM/TXD2/GPIO0 Pad Location P13 F12 F14 H12 L14 L15 N15 M15 K11 L11 M12 M11 M14 N14 L13 M13 L12 R05 R06 6 Product Documentation This section includes the related product documentation and references to information posted on Freescale's external web page. This document is labeled as the type: Data Sheet: Technical Data. Definitions for all Freescale document types are available at: http://www.freescale.com. You can also obtain information on the mechanical characteristics of the MCF5251 integrated microprocessor at http://www.freescale.com/digitalaudio. The following documents are required for a complete description of the device and are necessary for proper design: MCF5251 Reference Manual (order number: MCF5251RM) MCF5251 Product Brief (order number: MCF5251PB) 6.1 Revision History Table 21. Revision History Location Revision Removed MCF5251CDVM140, MCF5251CEVM140, MCF5251DVM140, MCF5251EVM140. Table 21 summarizes revisions to this document since the release of Rev. 2.1. Table 1 MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 Freescale Semiconductor 33 Product Documentation MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3 34 Freescale Semiconductor |
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